SiFive is a semiconductor company that designs and produces RISC-V-based processors and silicon chips. Founded in 2015 by researchers from the University of California, Berkeley, SiFive is probably the best-known IP company focusing on RISC-V. It operates a business model approximately the same as Arm
JPR’s David Harold met with John Ronco, SiFive’s GM and SVP, Product, to discuss the state of the RISC-V market, including chiplets, customization from a design point of view, and the potential of RISC-V to win further sockets from Arm.
John Ronco (Source: SiFive)
At a high level, is being a RISC-V-focused IP company the right business? It feels like there have been challenges. Early companies seemed quite Arm-like, entering deals only to be told their cores were worth a fraction of an Arm core. There’s also been a lot of shifting among RISC-V players to find where the value lies. What has SiFive’s experience been?
John Ronco: Do we believe in RISC-V’s future? Absolutely, yes. The question is, how long it will take? I haven’t met a customer who says they’re entirely content with Arm and don’t need an alternative. Every conversation revolves around when and how they want to adopt RISC-V, not if. The key is understanding how fast the RISC-V market grows and its eventual limits.
Every conversation revolves around when and how they want to adopt
RISC-V, not if.
In my view, RISC-V will eventually take over everything. It’s just a matter of time. The real question then becomes: Who will drive this adoption? Is there value in being a RISC-V IP provider? My answer is yes but with caveats. The market isn’t big enough for the number of players currently in it. Consolidation is inevitable. That said, IP remains a fundamentally attractive business, and we frequently hear dissatisfaction with Arm’s model, including its move toward chiplets and CSS (Compute Subsystems). Many customers value the flexibility RISC-V IP offers.
So, there’s a role for high-quality RISC-V IP providers, but not as many as there are today?
Ronco: Exactly. Delivering successful IP requires significant resources and a broad customer base. You can’t just do one or two deals and expect to sustain a business. At SiFive, we see RISC-V IP as both a vital business and our core mission. We aim to be the gold standard, offering a complete portfolio from low-end microcontrollers to high-performance cores for servers.
Early on, customization seemed like a big selling point for RISC-V. But it feels like that emphasis has waned. Companies still mention it, but it doesn’t seem to be a major focus anymore. What’s SiFive’s perspective?
Ronco: Customization exists on two levels. First, there are custom instructions at the ISA level. Second, there’s core configuration, where customers choose from a range of options to meet their performance, power, and area (PPA) targets. The latter—core configuration—remains very relevant. Customers don’t want a one-size-fits-all solution; they want standard RISC-V cores configured to suit their applications. We offer a broad portfolio with extensive configuration options, more so than Arm. While Arm is moving away from configurability, we still prioritize it.
We’ve deprioritized custom instructions in areas like low-end microcontrollers, where the benefits don’t justify the complexity. However, in fields like AI and accelerated compute, custom instructions can be valuable, especially when pairing a RISC-V processor with custom hardware accelerators.
Where does the burden of customization lie? Do you handle it as a service, or do customers take it on themselves?
Ronco: It’s mostly something we handle. We’ve streamlined the process so that customers choose from a detailed list of options, and we deliver a tailored solution. The challenge is managing that complexity, while keeping it efficient and scalable. Ultimately, it’s about offering variations on a theme, while maintaining a unified product line.
SiFive’s CES 2025 suite. (Source: SiFive)
Let’s talk about other compute elements in your portfolio. I’m particularly interested in the XM matrix engine. And how about GPUs built around RISC-V. Is that something SiFive is pursuing?
Ronco: GPUs are a whole conversation in themselves. While it’s possible to build a GPU with RISC-V processors and accelerators, it’s not a priority for us. We’re content to let others solve the GPU problem. Instead, we’re focused on AI and Tensor Cores.
Our portfolio spans from low-end microcontrollers to high-end, out-of-order cores. We also offer vector extensions for added performance. For higher-end applications, we pair vector cores with large matrix engines, enabling AI and accelerated computing solutions. This approach is more flexible and future-proof than fixed-function designs. It allows customers to leverage open-source software and adapt to evolving workloads.
Why introduce a matrix engine like XM? Was it customer demand or a strategic decision?
Ronco: Both. Customers were already pairing our vector cores with their own matrix engines. By developing our own, we offer an integrated solution that some customers find attractive. It’s a complementary product, not a replacement for vector cores. Some customers prefer to develop their own accelerators, while others want a ready-to-use solution. We’re happy to support both approaches.
It seems like you’re focusing on higher-end markets, like data centers and automotive. Is that accurate? Are you moving away from low-end RISC-V cores?
Ronco: Not entirely. Our strategy remains top to bottom. While low-end microcontroller cores don’t generate significant revenue, they’re an important part of our portfolio. Last year, we refreshed our embedded processor lineup, including the E2 (Essentials 2 series), which can be configured to cover Arm Cortex-M33 and M0+ use cases. These cores are often used alongside higher-end cores in the same SoC, simplifying integration and management.
That said, our focus is broader. Over the past year, we’ve announced products for data centers, AI, automotive, and embedded applications. This breadth is both a strength and a challenge, as we’re covering multiple markets simultaneously. Adoption rates vary by segment, but we’re seeing traction across the board.
What about hardening and chiplets? Is there market demand for hardening RISC-V IP into chiplets?
Ronco: There’s interest, but multi-vendor chiplets are still a work in progress. While single-vendor chiplets are gaining traction, widespread adoption of multi-vendor solutions will take time. Several customers are exploring this direction, but the ecosystem isn’t fully mature yet.
How do customers evaluate IP? Are development boards a focus, or do you prioritize other methods?
Ronco: Development boards are primarily for ecosystem and software development. They’re useful for showcasing improvements across generations, but most IP evaluation happens through FPGA, SystemC models, or emulation. Sometimes, customers simply take the RTL and evaluate it themselves. Development boards are more about enabling software development and fostering RISC-V adoption.
What have I missed—something crucial about SiFive you’d like to emphasize?
Ronco: The key point is that RISC-V is happening. Our mission is to grow the market and secure a fair share of it. There are too many IP vendors now, but consolidation will come. In the end, there will be a mix of in-house development, a few high-quality IP vendors, and niche players.
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