RED Semiconductor is a UK-based fabless semiconductor company that specializes in developing advanced microprocessors for AI and cryptography applications. The company’s primary offering is a new type of processor core called VISC (Versatile Intrinsic Structured Computing), which aims to enhance the performance of AI and security applications through a combination of abstraction, parallelism, and acceleration.
Transparency: I first encountered RED Semiconductor in 2023 and subsequently have advised the company on marketing and operations outside of my role at JPR.
I met with RED Semiconductor’s CEO, James Lewis, at IET (Institution of Engineering and Technology) on the banks of the Thames in London to get the latest update on the company. RED has recently joined the Silicon Catalyst accelerator (where, for full transparency, I’m also an adviser).
What’s the problem you’re trying to solve?
James Lewis: The challenge for developers and implementers of electronics today is the need to increase performance for real-time data processing from sensors. This includes making sense of surroundings and using that information to make useful decisions—whether that’s for artificial intelligence or machine learning—on continuous streams of data in real time.
This all needs to be done at a cost and power level appropriate for the application. Essentially, we’re talking about delivering high-performance real-time processing with low power consumption in a small form factor.
And this is RISC-V?
Lewis: Yes. Our technology is an accelerator for RISC-V that transforms a simple, in-order RISC-V architecture into a context-sensitive, out-of-order system.
The accelerator focuses on key tasks like signal conditioning, decision-making, encryption, and similar operations. We chose RISC-V because it’s open and allows us to work deeply with the architecture.
We take two approaches with our solution. The first is to embed our technology, which we call VISC, directly into the processor pipeline, making it fully integrated. The second approach is to configure it as a front-end accelerator for existing RISC-V cores.
VISC isn’t just hardware—it’s a set of abstracted instructions. These allow routines or even entire algorithms to be executed with a single call. Our front end acts like a hardware compiler, interpreting these abstracted instructions, reordering tasks, and optimizing both instruction execution and data flow. This ensures the processor pipeline is always fully utilized, avoiding wasted clock cycles.
How complex can these abstracted instructions get? And who decides which instructions to support? Can customers customize them?
Lewis: The more abstracted the instructions, the more specific they become to a customer’s requirements.
At the base level, we support mathematical functions like FFTs, DCTs, and others. But we can also provide highly abstracted instructions for entire algorithms. For example, a customer could request a single instruction for an error correction routine or a cryptographic key generation sequence.
These instructions make life much easier for developers. Instead of writing hundreds or even thousands of lines of code for complex routines, they can use a single instruction like “do error correction” or “generate key.” This abstraction allows for customer-specific implementations while simplifying development.
I see why you describe this as compiler-like. But there’s still a compiler involved, right? How does it work with VISC?
Lewis: Yes, we adapt widely used open-source compilers like LLVM to work with our high-level abstracted instructions. The compiler packages these instructions and metadata, which the VISC hardware interprets in real time.
In the future, as VISC becomes more integrated, this process will become even more seamless. VISC can decode directly into operations, further reducing latency and saving clock cycles.
How does your approach compare to existing architectures, like SIMD, vector processors, or other accelerators?
Lewis: VISC is versatile—that’s actually what the “V” stands for. Instead of locking the architecture into specific functions, like a matrix multiplication accelerator, it can accelerate anything that’s mathematically defined.
For example, RISC-V’s existing vectorization system introduces separate registers for scalar and vector operations, along with a completely new instruction set. This means you often waste time moving data between registers. With VISC, we avoid this by using the same register set for both scalar and vector operations.
Any scalar instruction in VISC can be vectorized simply by modifying it. We also incorporate SIMD capabilities, ensuring data within registers is optimally ordered for efficient processing. This adds an extra layer of parallelism without introducing inefficiencies.
You mentioned AI and cryptography earlier. What markets are you targeting?
Lewis: VISC can scale. However, our initial focus is on real-time, sensor-driven applications.
Examples include autonomous vehicles analyzing their environment, healthcare devices monitoring patients, or industrial systems making real-time decisions. These applications require high-performance, low-power, and real-time processing.
Cryptography is also critical in these applications. VISC excels at real-time secure data processing, making it ideal for boosting security without compromising performance.
How have you funded RED, and where are you now?
Lewis: RED is an old-school start-up in the best sense. The founders have driven it forward with their energy, expertise, and funding. Early contributors provided services in exchange for equity, allowing us to bootstrap the company.
About 15 months ago, we joined the UK’s Chip Start program, administered by Silicon Catalyst. This provided funding and support to move our business forward. We’ve since joined Silicon Catalyst’s two-year acceleration program, which gives us access to advisers, industry partnerships, and funding opportunities, particularly in Silicon Valley.
What’s the question people most often ask you about RED?
Lewis: People often ask, Why hasn’t this been done before? The answer is straightforward: Large companies like Arm and Intel are constrained by their legacy systems and large engineering teams. They can’t pivot or experiment as freely as a start-up can.
Start-ups like RED exist because we can reexamine old ideas, adapt them to modern needs, and innovate without the constraints of legacy systems.
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