Andrea Gallo from RVI speaks to JPR’s David Harold about RISC-V’s future. RISC-V is moving towards further standardization with the RVA23 Profile, ensuring software compatibility while retaining flexibility. AI and HPC are key focus areas, with new matrix extensions optimizing workloads. Gallo sees hardware-software co-design as the future, reinforcing RISC-V’s customization advantage over legacy architectures.
RISC-V International is the global nonprofit organization that oversees the development, standardization, and promotion of the RISC-V instruction set architecture (ISA). It was originally established as the RISC-V Foundation in 2015 but later incorporated in Switzerland as RISC-V International in 2020 to encourage international participation and avoid geopolitical restrictions.
We met with RISC-V International Vice President of Technology Andrea Gallo to find out what to expect from RISC-V in 2025.
At CES, there was talk about a shift away from customization towards more standardized and hardened RISC-V IP products. Have you observed this trend?
Andrea Gallo: At RISC-V International, we’re focusing on standardization through Profiles. With so many extensions being ratified, companies can customize their chips extensively, but they bear the cost of maintaining toolchains, libraries, and OS support. Profiles define a set of mandatory extensions for specific device classes, bringing binary compatibility across different RISC-V implementations.
For example, at the RISC-V Summit North America in October, we announced the ratification of the RVA23 Profile, which ensures software portability for modern, high-performance application processors. Recently at FOSDEM 2025, Canonical stated their intention to release Ubuntu builds for this Profile, which means that a single binary will run on all compliant chips. I anticipate that other distro vendors are also preparing builds for RVA23-compliant platforms. Features like hypervisor and vector processing are key components of RVA23, enabling virtualization for cloud and consumer applications and accelerated math performance for workloads including AI/ML and cryptography.
When do you expect to see products based on RVA23?
Gallo: Some members have announced they are close, and we should see products this year.
Some companies, like MIPS, have mentioned that moving from highly flexible, synthesizable soft IP towards more hard macros optimized for specific processes helps with security concerns. Is this shift towards hardened IP also influenced by Arm’s licensing strategy?
Gallo: Optimizing for a specific fabrication process, that approach can improve efficiency and security. While RISC-V International doesn’t work directly on chiplets, we see market demand for solutions that require less effort than fully custom soft IP with our members such as Tenstorrent and Ventana offering chiplet support.
Who are the biggest adopters of RISC-V today?
Gallo: We don’t collect royalties, so we often rely on data from trusted analyst reports to track adoption. Nvidia estimated that it would cover 1 billion RISC-V microcontroller cores in 2024, built into its chips. Additionally, The SHD Group has a new report coming out soon with adoption forecasts from now until 2030 across markets like consumer, computing, automotive, networking, and data centers.
There’s a perception that Arm dominates in software and tooling. How is RISC-V closing the gap?
Gallo: It’s changing rapidly. Major Linux distributions—SUSE, Canonical, Red Hat—report that 97–98% of their packages are already ported to RISC-V. Canonical shared their plans in a talk at FOSDEM to build Ubuntu for the RVA23 Profile, ensuring compatibility across devices. Major tool vendors are members of RISC-V and already have support enabled for the architecture.
What about high-reliability applications like automotive and aerospace?
Gallo: Automotive is a key focus, especially in Europe. The EU has funded several RISC-V initiatives, including a call for proposals targeting software-defined vehicles. Many RISC-V IP vendors have already achieved ISO 26262 safety certification. Our role is to help coordinate collaboration among members, identifying gaps and opportunities in areas like domain isolation and security. RISC-V technology is also being leveraged in space systems, ranging from satellites to deep space missions with members like Frontgrade Gaisler and Microchip offering silicon in this field.
RISC-V adoption in AI and HPC is growing. What technical challenges need to be addressed?
Gallo: HPC and AI are converging, and RISC-V is evolving to support both. We’re working on two approaches to matrix extensions. The integrated matrix extension embeds matrix instructions directly into the core, reducing latency. The attached matrix extension offers higher throughput by allowing multiple cores to share a larger external matrix unit. Each approach serves different needs—integrated is ideal for edge AI, while attached suits high-performance computing.
Are proprietary solutions like SiFive’s XM aligned with these efforts?
Gallo: Member contributions help shape our standards. Companies often develop their own solutions first and then contribute to standardization. I’d expect alignment between what’s already being developed and what we standardize. There was a great panel on RISC-V in HPC at the most recent RISC-V Summit North America.
Before we wrap up, is there anything else I should have asked?
Gallo: One key trend is workload-designed silicon. Companies are increasingly co-designing hardware and software for specific applications to achieve a more optimized complete solution. RISC-V enables this customization better than legacy architectures, making it ideal for AI, automotive, and IoT. Our members are optimizing RISC-V for workload-specific needs, whether CPU-bound, memory-bound, or I/O-bound applications. I recommend reading Nick Brown’s paper, which showcases RISC-V’s strong performance in real-world HPC workloads.
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