What next for SiFive?
We talk consolidation, competition, and customization.
Are spiking neural nets going to catch the little fish of AI?
A CES interview with Innatera execs.
White paper on RISC-V market insights
Is RISC-V really succeeding?
SiFive leads RISC-V segment
Expanded features and dev boards.
Arm’s power play will backfire
It was stupid to bring the dispute into the public arena.
RISC-V SoC with GPU from Eswin
Available on SiFive’s new developer’s board.
InspireSemi announces tape-out of RISC-V HPC chip
Thunderbird accelerated computing chip.
Imagination GPU joins SiFive CPU and in-house NPU in Eswin RISC-V edge computing SoC
RISC-V and a GPU, like chocolate and peanut butter—what could be better?
Could Raspberry Pi IPO be a boon for RISC-V?
And maybe even enable a better GPU?
Codasip announces L110 for power-efficient applications
New ‘bounded’ customization in tools.
Will Arm make it to the workstation world?
Ampere offers a dev kit to those who want to try.
Think Silicon demos GPUs for embedded, wearables
Working with Edge Impulse on ML for wearables and AIoT.