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AMD’s big cache exposed at Hot Chips

AMD changed the rules when it introduced its chiplet packaging approach and demonstrated it could beat Amdahl’s Law and scale-up processors. At Hot Chips 2021, they revealed a bit more about their packaging magic, and their 3D V-Cache uses a novel new hybrid bonding technique. This manufacturing scheme can create up to an impressive 192 MB of L3 cache per ...

Jon Peddie

AMD changed the rules when it introduced its chiplet packaging approach and demonstrated it could beat Amdahl’s Law and scale-up processors. At Hot Chips 2021, they revealed a bit more about their packaging magic, and their 3D V-Cache uses a novel new hybrid bonding technique. This manufacturing scheme can create up to an impressive 192 MB of L3 cache per CPU chip., At Computex, AMD showed a prototype Ryzen 5000 series processor with an additional 64 MB 7 nm SRAM stacked directly on top of the CPU core complex. When tested versus a stock 5900X at 4.0 GHz, they achieved
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